Description
The role is responsible for the physical implementation of design partitions from netlist through tapeout for a highly complex SOC using advanced process technology. Responsibilities include collaborating with design and physical-design teams, debugging constraints, facilitating logic changes, creating timing ECOs, developing analysis scripts and methodologies, documenting guidelines, analyzing timing paths, and implementing timing infrastructure. The minimum qualifications are a bachelor's degree and at least 10 years of relevant industry experience, with strong TCL programming skills; preferred qualifications include large-design STA and timing-closure experience, sub-micron SoC timing experience, noise and crosstalk modeling knowledge, circuit-modeling expertise, ECO implementation experience, and scripting experience in Perl or Python.
