Description
The role is responsible for the physical implementation of design partitions from netlist through tapeout for a highly complex SoC using advanced process technology. Responsibilities include collaborating with design and physical design teams, debugging timing constraints, creating timing ECOs, developing analysis scripts and methodologies, documenting guidelines, analyzing timing paths, and implementing timing infrastructure. The minimum qualifications are a bachelor's degree, at least zero years of industry experience, STA experience, and experience with noise, crosstalk, and/or OCV effects.
