Description
The role is responsible for the physical implementation of design partitions from netlist through tapeout for a highly complex SOC. Responsibilities include collaborating with design and physical design teams, debugging constraints, facilitating logic changes, creating timing ECOs, developing analysis scripts and methodologies, documenting guidelines, analyzing timing paths, and implementing timing infrastructure. The minimum qualifications are a bachelor's degree and at least three years of relevant industry experience, along with experience in large-design STA and timing closure and programming skills in Perl and TCL.
