SoC Physical Design Engineer, Top Level at Apple

Department: Hardware

Location: Beaverton, Oregon · Seattle, Washington
Type: Other
Level: senior
Posted: Sep 21, 2026

Description

Apple is hiring a Physical Design Engineer to implement complete chip design from netlist through tapeout. The role collaborates with FE and physical design teams, leads place-and-route execution and planning, resolves physical-design and flow issues, and drives methodologies and progress tracking. The position requires a minimum bachelor's degree and 10+ years of relevant industry experience, with extensive ASIC, SoC, IP, database, CAD, and process-related design expertise preferred or required.

Required Skills

Physical design
Place and route
ASIC integration
SoC design
Database management
Floorplanning
Timing verification

Additional Information

Minimum Education: Bachelor's degree
Required Previous Experiences: 10+ years of relevant industry experience
Experience integrating internal and external IP and driving physical-domain IP requirements
Experience with large SoC designs exceeding 20 million gates, 1 GHz frequencies, and sub-45 nm technologies
Detailed understanding of database management issues
Experience with floorplanning, place-and-route, global timing verification, and physical design verification flows
Preferred Qualifications: Familiarity with ASIC integration, including floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration
Experience with SoC issues involving multiple voltage and clock domains, ESD strategies, mixed-signal block integration, and package interactions
Familiarity with hierarchical and top-down design, budgeting, timing, and physical convergence
Familiarity with design-for-yield and manufacturability, multi-Vt strategies, and thermal management
Translation Company Name: Apple

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