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SoC Physical Design Verification Engineer at Apple

Department: Hardware

Location
Beaverton, Oregon · San Jose, California
Level
entry
Posted

Description

Apple is hiring a Physical Verification Engineer to join its Silicon Technologies group and help design and manufacture a high-performance, power-efficient system-on-chip. The role performs chip- and block-level physical verification checks including LVS, DRC, design-for-manufacturing, design-for-yield, and lithography; collaborates with CAD, technology, implementation, package, and floorplan teams; supports flow bring-up, validation, and tapeout signoff; and leads schedules and cross-functional engineering efforts. The minimum qualification is a BS degree with zero years of relevant industry experience.

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