SoC RTL Design Engineer at Quadric

Department: Hardware Engineering

Language

Compensation

CA$175,000 – CA$230,000/yr

Setup: Remote - Canada
Type: Full-time
Level: staff+
Posted: Sep 21, 2026

Description

Quadric is hiring a Staff SoC RTL Engineer to join its chip design team and contribute across SoC architecture, subsystem development, third-party IP integration, PPA optimization, and timing closure. The role requires a degree in electrical or computer engineering, at least five years of SoC/ASIC front-end design and integration experience, proficiency in SystemVerilog or Verilog, and expertise in computer architecture, low-power digital design, and at least one SoC subsystem. The position offers a base salary of $175,000 to $230,000, equity, a discretionary annual performance bonus, and medical, dental, and vision insurance from day one.

Required Skills

SystemVerilog
Verilog
SoC/ASIC design
PPA optimization
Timing closure
Low-power design
Co-simulation

Additional Information

Minimum Education: Bachelor's, master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field
Required Previous Experiences: At least 5 years of hands-on SoC/ASIC front-end design and integration experience
Experience with SoC subsystems and third-party IP, including VCS and Verilog/C co-simulation
Preferred Qualifications: Experience in logic synthesis and performance modeling
Experience in FPGA design
Familiarity with automotive safety and hardware security standards
Translation Company Name: quadric, Inc