Description
Google is hiring an SoC Static Timing Signoff Engineer to deliver system-on-chip static timing analysis, define timing signoff process corners and uncertainties, manage clock-tree jitter and implementation, validate full-chip timing constraints, create timing ECOs, and oversee final SoC signoff. The role requires a bachelor's degree in Electrical Engineering or Computer Science or equivalent practical experience, eight years of silicon timing closure and chip integration experience, static timing tool experience, and experience delivering silicon. Preferred qualifications include a master's degree, ASIC design-flow experience, semiconductor device physics knowledge, and scripting skills.
