Description
The Senior DFT Engineer will design, implement, and verify DFT architectures for complex SoCs, including scan, MBIST, LBIST, boundary scan, scan insertion, test compression, ATPG, memory and logic BIST, and UPF/CPF-based low-power DFT. The role collaborates with RTL, physical design, ATE, and verification teams to integrate DFT, perform RTL and gate-level verification, develop test programs, and optimize test coverage, pattern count, and test time. Required skills include DFT methodologies, ATPG tools, fault models, physical design constraints, and silicon debug and ATE bring-up; a bachelor’s or master’s degree in Electrical or Electronics Engineering is required.
