Description
Renesas is hiring a Senior Engineer to develop and maintain design-enablement methodologies for RTL design teams. The role focuses on Lint, CDC, and RDC signoff flows, automation of checks and workflows, collaboration with design teams, creation of guidelines and best practices, and debugging RTL and static issues. The position requires strong RTL design and static verification expertise, with Verilog or SystemVerilog, Tcl and shell scripting, and Python experience preferred. The role follows a hybrid model with remote work two days per week and office collaboration on Tuesdays through Thursdays.
