Sr. FPGA Developer (Hybrid- Aberdeen Proving Ground, Maryland) at Fairwinds Technologies

Compensation

$150,000 – $175,000/yr

Setup: Hybrid
Location: Middletown, Delaware · Aberdeen Proving Ground, Maryland
Type: Full-time
Level: senior
Posted: Sep 22, 2026

Description

Fairwinds Technologies is hiring a full-time FPGA Design Engineer for a hybrid role at Aberdeen Proving Ground, Maryland. The position focuses on developing and validating programmable logic for RF signal processing, high-speed data movement, DSP algorithms, and wideband RF applications using Xilinx Vivado, Verilog, VHDL, and Zynq UltraScale+ RFSoC, MPSoC, and Versal platforms. Responsibilities include RTL design, simulation, synthesis, timing closure, debugging, system integration, test-bench development, and support for prototype-to-production transitions. The role requires a bachelor’s degree, 10+ years of FPGA design experience, U.S. citizenship, and a Secret-level security clearance or ability to obtain one.

Required Skills

Xilinx Vivado
Verilog
VHDL
RTL design
Timing closure
AXI protocols
JTAG debugging
RF signal processing
Fixed-point optimization

Additional Information

Minimum Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field
Required Previous Experiences: 10+ years of FPGA design and development experience
Hands-on Xilinx Vivado synthesis, implementation, timing closure, and debugging experience
Hands-on Xilinx Zynq UltraScale+ RFSoC experience; Versal and other UltraScale+ experience preferred
FPGA design experience for PCB-based embedded systems
Experience implementing DSP designs provided by DSP engineers
FPGA debugging experience with ILA, VIO, and JTAG
Experience integrating FPGA designs with high-speed data converters
Experience designing multi-sample-per-clock architectures for high-throughput signal processing
Fundamental RF signal processing knowledge
Preferred Qualifications: Versal ACAP architecture experience
High-speed interface experience in RF data converter applications
DSP and fixed-/floating-point implementation knowledge
FPGA power optimization and performance tuning
Tcl or Python scripting for build automation and CI
DoD SBIR or government-funded R&D experience
Xilinx RFSoC integrated RF data converter experience
Analog Devices reference design and evaluation platform familiarity