Description
Renesas is hiring a Mask Layout Engineer to design and develop mask layouts for next-generation low-voltage and medium-voltage shielded-gate trench MOSFET technologies. The role includes chip layout design using Virtuoso, mask design-rule verification with Calibre, T/O procedures, schedule adjustment, provenance tracking, mask specification definition, scribe and accessory layout, and shot-map documentation. The position requires more than five years of mask layout design experience for power semiconductor devices, communication skills with product and process technology engineers, and intermediate English and Japanese proficiency. The role follows a hybrid work model with two remote days and office collaboration on Tuesdays and Wednesdays.
