Sr.Principal Digital IP Engineer at NXP

Location: Bengaluru, Karnataka
Level: not_specified
Posted: Jun 22, 2026

Description

The role develops reusable intellectual property for SoC and subsystem integration, moving designs from concept through silicon. Responsibilities include defining micro-architecture, developing RTL in Verilog, SystemVerilog, or VHDL, optimizing for power, performance, and area, performing lint, CDC, synthesis, and STA checks, fixing bugs, supporting design reviews and sign-off, and collaborating with verification teams. The position requires strong RTL design experience, SoC/IP design and integration knowledge, experience with lint, CDC, synthesis, and timing analysis, and low-power design experience.

Required Skills

RTL design
Verilog/SystemVerilog/VHDL
SoC/IP integration
Lint
CDC
Synthesis
Timing analysis
Low-power design

Additional Information

Required Previous Experiences: Strong RTL design experience using Verilog, SystemVerilog, or VHDL
SoC/IP design and integration experience
Hands-on experience with lint, CDC, synthesis, and timing analysis
Low-power design experience
Preferred Qualifications: Full-cycle IP/SoC development experience
Formal verification or low-power flow exposure
Post-silicon validation and bring-up experience
Translation Company Name: IN61 NXP India Private Limited