Sr Staff ASIC Verification Engineer at Synopsys

Synopsys is seeking a senior IP verification leader to own verification for major DesignWare IP blocks, subsystems, or cross-project methodologies from architecture through signoff and customer delivery. The role defines verification strategy and signoff criteria, leads technical execution and coverage closure, applies AI-assisted verification techniques, builds reusable UVM environments, and mentors verification engineers. Candidates need an electrical or electronics engineering degree with 8+ years of IP or SoC verification experience, or an MS with 6+ years, along with expertise in UVM, SystemVerilog, simulators, and complex IP verification.