Description
The role involves understanding design functionality, designing and developing verification environments, improving verification architecture and flow, running RTL and gate-level simulations and daily regression, and developing, analyzing, and closing code and functional coverage. It requires a bachelor's or master's degree in computer science or mechanical engineering, at least five years of experience, familiarity with SystemVerilog and UVM, and experience with test plans, test benches, assertions, debugging, and verification tools. Additional qualifications include IC verification, logic and circuit design, Python scripting and automation, C/C++/Java, software design patterns, and mixed-signal verification.
