Description
Synopsys is hiring a Senior Staff Digital Verification Engineer focused on memory interface IP, including HBM, DDR, LPDDR, and AMBA. The role involves designing SystemVerilog and UVM verification environments, developing test plans and reusable verification IP, driving functional coverage closure, debugging with simulation tools, collaborating with design and architecture teams, and mentoring junior engineers. Candidates need a bachelor's or master's degree in electrical or computer engineering, 6 to 8+ years of ASIC or SoC verification experience, and proven experience verifying memory interface protocols in production-level designs.
