Description
Synopsys is hiring a senior SERDES analog IC design engineer to architect and design multi-gigabit NRZ and PAM4 transceiver circuits for advanced FinFET and gate-all-around processes. The role covers SERDES standards, analog and mixed-signal sub-blocks, analog-digital co-design, calibration, timing handoff, layout collaboration, simulation, post-silicon bring-up, customer silicon analysis, and mentoring. Candidates need an MTech or MS with 8+ years or a BTech or BS with 10+ years of hands-on analog IC design experience, including CMOS tape-outs in FinFET technologies and demonstrated multi-gigabit NRZ and PAM4 design experience.
