Sr. Staff Engineer – Processor Verification and Compiler Validation at Enphase Energy

Compensation

$135,000 – $205,200/yr

Location: Fremont, California
Type: Full-time
Level: senior
Posted: Sep 11, 2026

Description

Enphase Energy is hiring a Verification Engineer to validate a custom RISC-V VLIW processor architecture and its associated instruction set extensions. The role develops SystemVerilog verification environments, validates pipeline, scheduling, memory, exception, and architectural behavior, supports hardware/software co-verification, and contributes to mixed-signal verification environments involving RTL, real-number modeling, analog simulation, and closed-loop control applications. Candidates need a relevant PhD with 5+ years of industry experience or a Master's degree with 8+ years of experience, along with processor architecture, SystemVerilog, debugging, Python, and RTL verification expertise. The base salary is $135,000 to $205,200, with stock, bonus, and benefits.

Required Skills

RISC-V VLIW
SystemVerilog
Instruction scheduling
Python
RTL simulation
Mixed-signal verification
Debugging

Additional Information

Minimum Education: PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or a Master's degree in a related field.
Required Previous Experiences: 5+ years of relevant industry experience with a PhD, or 8+ years with a Master's degree.
Experience developing SystemVerilog verification environments and industry-standard verification methodologies.
Experience analyzing instruction traces, execution timing, and architectural behavior.
Familiarity with RTL design, simulation, synthesis, and verification workflows.
Preferred Qualifications: Experience with RISC-V processors and ecosystem tools.
Experience with VLIW architectures, superscalar processors, or instruction scheduling concepts.
Understanding of compiler internals, code generation, optimization techniques, and scheduling algorithms.
Experience validating custom instruction set extensions.
Familiarity with deterministic real-time systems and safety-critical embedded applications.
Exposure to functional safety standards and methodologies.
Experience with SystemVerilog Real Number Modeling and mixed-signal verification.
Experience integrating RTL simulation with analog simulators and behavioral system models.
Knowledge of digital control systems, feedback control theory, power electronics, or power conversion systems.
Experience implementing C/C++ reference models and architectural golden models.
Familiarity with coverage-driven verification, formal verification, or constrained-random methodologies.
Experience building infrastructure for trace analysis, automated triage, and large-scale regression management.