Description
Synopsys is hiring a senior analog PHY design engineer to define and design analog and mixed-signal circuits for UCIe die-to-die interfaces and other high-speed I/O standards. The role covers transmitter and receiver architectures, equalization, clocking, calibration, behavioral modeling, PVT and reliability verification, package and signal-integrity analysis, layout and sign-off, silicon bring-up, lab characterization, and cross-functional collaboration. Candidates need a bachelor's or master's degree in electrical or electronics engineering or equivalent practical experience, 8 to 15 years of analog or mixed-signal IC design experience focused on high-speed interfaces, and strong expertise in Cadence Virtuoso, Spectre, Synopsys Custom Compiler, or HSPICE.
