Description
Qualcomm is hiring a Packaging Engineer to lead Far-BEOL wafer-bumping process integration, qualification, and high-volume readiness across silicon technology nodes, foundries, bumping lines, and OSATs. The role owns bumping process flows, process windows, DOE optimization, yield and reliability improvements, bumping house and line bring-up, and multi-source capacity expansion, while partnering with foundries, OSATs, and internal package, process, quality, test, and product development teams. The position requires 8–10 years of hands-on silicon interconnect, bumping, or RDL experience and a bachelor's, master's, or PhD in a relevant engineering field, with a pay range of $191,800 to $287,800.
