Description
Apple is hiring an ASIC STA Engineer to lead timing closure for full-chip and block-level System-on-Chip designs, develop timing verification and closure methodologies, generate timing constraints, and resolve complex timing issues across deep-sub-micron mobile SoCs. The role requires collaboration with multiple SOC teams and involves ASIC design, STA tools, scripting, and timing analysis. A bachelor's degree and three years of experience are required; digital design fundamentals, TCL and Perl scripting, STA tools, and timing-related knowledge are preferred.
