Description
Apple is hiring an ASIC STA Engineer to lead timing closure and constraints for full-chip and block-level SoC designs. The role collaborates with SoC design, verification, DFT, architecture, physical design, CAD, and flow teams to execute design and integration tasks, develop timing-analysis methodologies, and improve front-end design flows. The position requires a bachelor's degree and zero years of experience, with digital design, ASIC timing, scripting, STA tools, and front-end methodology experience preferred.
