Description
NVIDIA is hiring a STA Physical Design Engineer for its Networking DFT team to execute static timing analysis across RTL-driven constraints, DFT constraints, timing environments, models, ECO generation, and sign-off. The role also involves participating in flow development and working on challenging high-speed communication chip designs. Candidates should have a B.Sc. in Electrical or Computer Engineering, 2–3 years of STA engineering experience, strong communication skills, and adaptability; knowledge of physical design, DFT, timing closures, CDC, and EDA tools is advantageous.
