Description
Samsung Semiconductor Inc. is hiring a Senior/Staff PLL Designer to design RF/analog PLL and clocking circuits, SerDes analog PHY circuits, and high-performance clocking subsystems for RF transceivers, SerDes, and high-speed I/O applications in advanced deep-submicron CMOS technologies. The role includes system modeling, design verification, production support, and collaboration with digital and software developers. Candidates need a bachelor’s degree with 10+ years of experience, a master’s degree with 8+ years, or a PhD with 5 years of related experience, along with hands-on PLL and clock-generation circuit design, IC design CAD, Verilog/SystemVerilog, layout, and lab-testing skills. The base pay range is $163,000–$253,000 USD, with medical, dental, vision, and 401(k) benefits.
