Staff Application Engineer – ECO Timing at Synopsys

Location: Hyderabad, Telangana
Level: senior
Posted: Sep 21, 2026

Description

Synopsys is hiring an ECO Field Engineer in Hyderabad to work with semiconductor customers on timing signoff, physical design, extraction, ECO, and design closure for live silicon projects. The role involves diagnosing complex timing and physical design issues, deploying advanced-node design methodologies, delivering technical training and product demonstrations, supporting projects through tapeout, and automating workflows with TCL and Perl. Candidates need a BS or MS in a relevant technical discipline, 6–8 years of semiconductor design experience, expertise in STA, P&R, extraction, and ECO, and strong scripting and ASIC design knowledge.

Required Skills

Timing signoff
P&R
STA
Extraction
ECO
TCL
Perl
Parasitic annotation
ASIC design

Additional Information

Minimum Education: BS or MS in Electrical Engineering, Computer Engineering, or an equivalent technical discipline
Required Previous Experiences: 6–8 years of hands-on semiconductor design experience, including Place & Route, Static Timing Analysis, extraction, and Engineering Change Order flows
Experience executing silicon chip projects through physical design and timing closure on advanced technology nodes such as 7nm, 5nm, or 3nm
Strong TCL and Perl scripting experience for automating design tasks and building custom flows
Solid understanding of ASIC design flow, VLSI fundamentals, and CAD engineering principles across the full design cycle
Preferred Qualifications: Experience working directly with customers or cross-functional teams in technical support, applications engineering, or field engineering