SiFive is seeking a Staff Design Verification Engineer to lead the verification of cache and memory-subsystem functionality, focusing on cache coherency, ordering, correctness, and integration. This independent contributor role involves owning verification planning and execution, developing robust environments, debugging complex issues, and contributing to improved verification methodologies.
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RISC-V
SiFive delivers high-performance, scalable processor core IP solutions using the open RISC-V standard, with flexible customization and power efficiency. Its products include customizable scalar, vector, and matrix solutions, including scalable AI matrix engines for companies developing custom AI solutions and systems for edge IoT, consumer devices, autonomous vehicles, and data centers. SiFive IP powers over 2 billion devices worldwide and has achieved 400+ RISC-V design wins.