Staff Design Verification Engineer - Coherent Interconnect at ARM

ARM is seeking a Design Verification Engineer to build verification plans and strategies, collaborate with architects and designers, develop SystemVerilog/UVM test benches, create stimulus and coverage, debug functional regression failures, and improve verification methodology. The role requires a degree in Electrical/Computer Engineering or Computer Science, at least 8 years of verification or RTL design experience, CPU microarchitecture knowledge, and experience with constrained-random SystemVerilog/UVM testbenches. The salary range is $198,100-$268,000 per year, with hybrid working arrangements determined by team needs.