Description
Astera Labs is establishing a strategic R&D center in Israel and is hiring a Staff DFT Engineer to own the design-for-testability lifecycle for complex semiconductor chips. The role covers DFT architecture and strategy, JTAG/iJTAG, MBIST, scan, and ATPG methodologies, test-pattern generation and optimization, static timing analysis, gate-level simulation, test coverage, and cross-functional collaboration with architecture, verification, and backend teams. The position requires a bachelor's degree in electrical engineering or a related field, at least eight years of semiconductor DFT experience, expertise in DFT flows and EDA tools, and scripting proficiency; a master's degree, high-speed interface knowledge, chip bring-up experience, and advanced-process experience are preferred.
