Renesas is hiring a Digital Design Engineer with DFT capabilities to design and implement DFT architectures for SoC/ASIC products. The role requires at least five years of hands-on experience with scan, boundary scan, MBIST, low-power DFT, test coverage analysis, production test programs, timing constraints, ATPG, and RTL. The position is part of Renesas’ global semiconductor team and offers a remote work option.
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