Description
Renesas Electronics is hiring a Staff Digital Design Engineer in Chandler, Arizona to design and integrate low-power digital RTL for mixed-signal data conversion and power-management products. The role covers ASIC design flow, synthesis, timing and power analysis, P&R collaboration, DFT, verification, silicon evaluation, and technical leadership, including mentoring and recruitment support. Candidates need more than 10 years of digital design experience, an engineering degree, strong Verilog/SystemVerilog and ASIC skills, and the ability to travel domestically or internationally.
