Description
Micron Technology is hiring an ASIC IP STA Engineer in Bengaluru, India, for 6–10 years of experience. The role focuses on post-layout static timing analysis, timing closure, and signoff for high-speed memory and interface IPs such as DDR PHY, ONFI PHY, and IO Expander. Responsibilities include timing constraint development and debugging, Liberty and ETM model generation, SDF and gate-level simulation support, setup/hold and SI-aware signoff, and cross-functional collaboration with IP, SoC synthesis, and SoC physical design teams. The position requires strong Cadence digital implementation and signoff flow experience, TCL or Python proficiency, and familiarity with AI/ML-enabled EDA methodologies.
