Description
The role performs SOC physical design activities across floor-planning, partitioning, placement, clock tree synthesis, routing, and physical verification, including LVS, DRC, ERC, and antenna checks. Responsibilities include meeting congestion, timing, and area metrics, performing equivalence checks, STA, crosstalk and noise analysis, power optimization, and implementing timing and functional ECOs. The candidate should have formal verification, timing analysis, ECO implementation, and global-team experience, with Innovus, Encounter, ICC, Caliber, LEC, and Primetime experience desirable. The role requires independent work, guidance of team members, adaptability, and strong communication skills.
