Description
The Analog/Hard-IP Modelling Engineer will lead or participate in planning the modelling of analog and hard IP using Verilog and SystemVerilog, and contribute to modelling support for pre-silicon validation. The role requires strong knowledge of Verilog, SystemVerilog, UVM, digital verification, dotlib generation, and AMS or digital block modelling, along with experience mentoring junior engineers. A BS/MS in Electrical Engineering and 4–11 years of experience depending on the degree are required; MSV simulation, analog circuits, automation, and formal verification are advantageous.
