Description
Micron Technology is hiring a NAND Memory Design Engineer to perform block- and subsystem-level NAND array design, timing optimization, layout supervision, full-chip floorplanning, waveform finalization, and circuit optimization from base cells through full-chip level using HSPICE, Fast SPICE, and ncVerilog. The role also involves supporting array functionality, mentoring junior designers, documenting micro-architecture specifications, and applying AI-assisted tools while reviewing AI-generated outputs. Candidates need an MS or PhD plus 2–6 years of semiconductor experience, or a BS plus 6–10 years, along with deep knowledge of digital, analog, mixed-signal, CMOS, flash, reliability, and NAND memory technologies.
