Description
Renesas is hiring a Physical Design Engineer to lead MCU, subsystem, and block-level closure for complex hierarchical SoCs at advanced nodes. The role covers timing closure, congestion resolution, power integrity, physical implementation, clocking and floorplanning collaboration, UPF, automation, risk mitigation, and mentoring physical design engineers. Candidates need an M.Tech or B.Tech in Electrical Engineering, at least 7 years of physical-design experience, expertise in SoC closure and physical-design tools, and proficiency in Tcl, Python, or Perl.
