Staff Engineer - Physical Design at Synopsys

Synopsys is hiring a UCIe Physical Design Engineer to own the physical design implementation of UCIe PHY blocks and testchips from floorplanning through tapeout on 5nm and more advanced nodes. The role leads synthesis, place-and-route, timing closure, physical verification, design reviews, tradeoff analysis, flow pilots, and mentoring, while collaborating with verification, DFT, IP, foundry, and customer teams. Candidates need 4 to 7 years of ASIC physical design experience, multiple tapeouts and signoffs in 5nm or more advanced nodes, and expertise with DC, PT, ICC2/FC, and ICV.