Description
Astera Labs is establishing a strategic R&D center in Israel and is hiring a Physical Design Engineer specializing in SoC EMIR. The role owns backend power methodologies for complex semiconductor chips, including IR drop and signal/power electromigration analysis, power integrity collaboration, chip-package co-analysis, and root-cause analysis of voltage-drop and EM risks. The engineer will work in advanced FinFET process nodes and support the performance and yield of high-performance connectivity silicon.
