Staff Subsystem verification engineer at ARM

Arm is hiring a Staff Subsystem Design Verification Engineer to verify complex subsystems for next-generation Arm-based platforms. The role owns verification from planning through closure, develops reusable verification environments and automation, validates subsystem functionality across functional, integration, stress, and performance scenarios, and collaborates with architecture, design, firmware, emulation, FPGA, validation, and post-silicon teams. The position requires a relevant bachelor's or master's degree and at least 10 years of IP or subsystem verification experience, along with strong knowledge of Verilog, SystemVerilog, UVM, AMBA protocols, memory hierarchy, and related verification practices.