Description
Synopsys is hiring a Staff Verification Applications Engineer to drive customer deployments of VCS and Verdi simulation and debug technology, diagnose complex verification issues, develop automation scripts, and support competitive engagements. The role requires a bachelor's or master's degree in electronics engineering or a related field, 5–12 years of verification or applications engineering experience, and expertise in VCS, Verdi, SystemVerilog, UVM, SVA, Low Power UPF, and Gate Level Timing. The engineer will work directly with customers, collaborate with global R&D and product teams, and may travel for onsite engagements.
