Description
The Standard Cell Design Methodology and Flow Engineer will support a processor design effort by developing and integrating standard-cell design flows, coordinating with CAD, technology, and foundry teams, and contributing to library development. The role involves implementing digital blocks in Verilog or SystemVerilog, running simulations and formal checks, analyzing timing, power, and area data, and applying machine learning to detect quality issues. The minimum qualification is a bachelor's degree and at least 10 years of relevant industry experience.
