Description
The employer is hiring a Static Timing Analysis / Timing Closure & Signoff Engineer to support a leading global SoC manufacturer on advanced-node designs. The role owns timing constraints, block- and full-chip timing signoff, setup/hold and transition/capacitance closure, signal integrity, parasitic correlation, variation-aware analysis, hierarchical timing, low-power timing, and automation using TCL, Python, or Perl. Candidates need 3–8 years of relevant STA or physical design experience, a relevant engineering degree, and strong knowledge of Synopsys PrimeTime, SDC, MMMC, and advanced FinFET technology nodes.
