Static Timing Analysis (STA) Engineer at Altera

Altera is hiring a Static Timing Analysis (STA) Engineer to support timing closure and analysis for advanced FPGA designs. The role performs setup/hold and constraint analysis, debugs timing violations, develops timing constraints, collaborates with RTL, synthesis, and physical design teams, and supports performance, power, and area optimization. Candidates need at least six years of STA experience for ASIC or FPGA designs, familiarity with industry-standard tools and design flows, and a bachelor’s or master’s degree in a relevant engineering field. The position is based in Toronto, Ontario, Canada, with an estimated salary range of $102,900 to $149,100 CAD.