Static Timing Analysis (STA) Engineer at Astera Labs

Astera Labs is expanding its operations by establishing a strategic R&D center in Israel to develop complex semiconductor chips aimed at solving critical 'data bottlenecks' for scalable AI. This role involves taking significant technical ownership in a new site, focusing on Static Timing Analysis (STA) for chips powering advanced AI clusters. The engineer will be responsible for executing STA methods, bridging gaps between various design teams, managing SDC constraints, analyzing clock distribution network challenges, and contributing to design method improvement.