Description
Arm is hiring a Subsystem Design Verification Engineer to verify complex subsystems for next-generation Arm-based platforms. The role owns verification from planning through closure, develops reusable verification environments and automation, validates functionality across integration, stress, and performance scenarios, debugs RTL and testbench issues, and collaborates with architecture, design, firmware, emulation, FPGA, validation, and post-silicon teams. Candidates need a relevant bachelor's or master's degree, 2–4 years of IP or subsystem verification experience, and strong skills in Verilog, SystemVerilog, UVM, AMBA, C/C++, scripting, coverage closure, and RTL/testbench debugging. The role uses a hybrid working model.
