Description
Arm is hiring a Senior Subsystem Design Verification Engineer to verify complex subsystems for next-generation Arm-based platforms. The role covers verification planning, functional and integration testing, coverage closure, reusable verification environments, automation, debugging, and collaboration with architecture, design, firmware, emulation, FPGA, validation, and post-silicon teams. Candidates need a relevant bachelor's or master's degree and 4–9 years of IP or subsystem verification experience, along with strong knowledge of Verilog, SystemVerilog, UVM, AMBA protocols, memory hierarchies, C/C++, and RTL/testbench debugging.
