Description
Synopsys is hiring a System Level Test Engineer to own system-level silicon validation of DDR, LPDDR, and HBM memory interface IP in a Nepean lab. The role brings up silicon and reference platforms, characterizes timing and signal integrity, debugs failures, automates validation pipelines with Gitlab, and supports customer system debugging. Candidates need a bachelor’s or master’s degree in electrical or computer engineering or a related field, 3–5 years of silicon validation or system-level lab debugging experience, hands-on silicon or board bring-up experience, and knowledge of DRAM protocols, JEDEC timing, and signal-integrity basics.
