Description
Astera Labs is hiring an experienced Analog Mixed-Signal (AMS) Layout Engineer to perform full-custom layout of high-speed SerDes and other analog and mixed-signal circuits for next-generation transceiver intellectual property targeting TSMC 3nm. The role covers floorplanning, routing, parasitic minimization, DRC/LVS/ERC and EM/IR signoff, parasitic extraction, post-layout simulation, and collaboration with circuit, physical design, and digital implementation teams. Candidates need a bachelor’s or master’s degree in electrical engineering, microelectronics, or a related field, at least seven years of custom analog or mixed-signal layout experience in deep-submicron or FinFET processes, and expertise with tools such as Cadence Virtuoso XL and Calibre.
