Description
Astera Labs is hiring a Lead Digital Design Engineer in Bengaluru, India, to lead the architecture, RTL design, integration, and silicon bring-up of complex digital IPs and SoC subsystems for AI infrastructure products. The role requires strong Verilog/System Verilog expertise, ASIC design-cycle experience, knowledge of high-speed interfaces and protocols, and the ability to mentor engineers and lead technical execution. Preferred experience includes CXL, PCIe, Ethernet, AXI, DMA, packet processing, cache coherency, memory controllers, and high-speed interconnects.
