Description
Astera Labs is hiring Senior Digital Design Engineers to develop micro-architecture and front-end circuit design for high-performance network controllers. The role covers RTL, synthesis, IP integration, block-level verification, timing closure, DFT, silicon bring-up, and debug, with a focus on high-speed protocols such as PCIe, Ualink, Esun, and Ethernet. Candidates need an electrical engineering background, at least three years of experience with complex SoC or silicon products, and the ability to work immediately in the United States.
