Description
Astera Labs is hiring a Tech Lead Engineer, Design Verification to define and deliver verification for next-generation connectivity silicon supporting rack-scale AI infrastructure. The role leads verification planning, UVM-based SystemVerilog testbench development, coverage closure, regression automation, debugging, and silicon readiness for PCIe, UALink, and related high-speed protocols. Candidates need a bachelor’s degree in a relevant technical field, 5–8 years of ASIC or SoC design verification experience, and strong SystemVerilog and UVM expertise. The salary range is $175,500 to $195,000, with possible discretionary bonus, incentives, and benefits.
