Department: Compute Connectivity Engineering 1Education: education_required
Astera Labs is seeking a Tech Lead, Formal Verification Engineer to spearhead formal verification initiatives for intricate IP and SoC designs. The role involves developing and executing formal verification plans, driving proof convergence, and ensuring design correctness. The ideal candidate will collaborate with various internal teams to achieve first-pass silicon success for Astera's cutting-edge connectivity and AI infrastructure products.
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AI InfrastructureSan Jose, CA, United States
Astera Labs builds silicon-based hardware connectivity solutions and software for rack-scale AI, including smart fabric switches, retimers, memory controllers, and signal conditioners. Astera Labs reported second-quarter 2026 revenue of $392.4 million, up 27% quarter over quarter and 104% year over year.